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intelfpgaintel-fpga

NIOSII with Remote System Update IP Core for Cyclone10LP does not execute

I am working on an update procedure for the Cyclone10LP FPGA with Quartus Prime 20.1.1. The platform design is done the following.

Platform Design

The NIOSII Software Build tool for Eclipse Project is configured according to the .sopcinfo file. The NIOSII soft core works properly.

However, executing the Altera provided HAL function altera_remote_update_trigger_reconfig(...) does not trigger the Remote System Update (RSU) for reconfiguration. A verification of the RSU was also done with discrete logic, there it works properly.

My code looks like the following.

int main()
{
    altera_remote_update_state sp;
    sp.base = REMOTE_UPDATE_0_BASE;
    usleep(500000);
    altera_remote_update_trigger_reconfig(&sp, 1, 0x800000, 0);
    /* Event loop never exits. */
    while (1);
    return 0;
}

Any idea why the RSU does not work?

Solution

  • Verify, if the right address offset is used in the altera_remote_update_regs.h according to the Remote Update Intel FPGA IP User guide.

    I had to adapt the address offsets of the registers. (Hint: the RU_BOOT_ADDRESS register from the User guide is the ALTERA_RU_PAGE_SELECT_REG in the altera_remote_update_regs.h.) It seems that the board support generation does not adapt all the needed parts.

    Further details about the RSU on the basis of a Cyclone iV see: http://billauer.co.il/blog/2017/06/remote-update-intel-fpga-cyclone-iv/