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verilog

Bit width calculation

I'm trying to understand "bit overflow" so I made a simple example.

As I understand, hex value 'hFF can convert to 7'b11111111

So I implement to check with $display("%b" , {7'hff});

But, I got the below warning message.

$display("%b" , {7'hff}); 
                         |
xmvlog: *W,INTOVF (testbench.sv,18|25): bit overflow during conversion from text [2.5(IEEE)] (7 bits).

How do I calculate the bit width, and why does the bit overflow warning message happen?

Solution

  • The "bit overflow" message happens because you specified 7 as the bit width, but your numeric literal (ff) requires 8 bits.

    As I understand, hex value 'hFF can convert to 7'b11111111

    No, 'hFF converts to 8'b11111111. If you count the number of 1's, you have 8.

    Verilog syntax supports the underline character as a visual separator to make it easier to understand numeric literals with several digits. For example, you could write the number as 'b1111_1111. That makes it easier to see that there are 8 1's.

    To avoid the warning, use 8'hff.

    The maximum 7-bit hex value is 7'h7f.