Simple assignment of wire to output led in verilog doesn't synthesis with yosis

Question

The following code will not build exiting with Error Code -6

module and_gate (
    input   [1:0]   io_button,
    output  [2:0]   io_led
);

wire wire1;
assign wire1 = io_button[0];
assign io_led[0] = wire1;

endmodule

But making this small change builds properly. Can you not just assign a wire to an output without modifying it in some way?

module and_gate (
    input   [1:0]   io_button,
    output  [2:0]   io_led
);

wire wire1;
assign wire1 = io_button[0];
assign io_led[0] = ~wire1;

endmodule

Answer 1

I've seen this before. Some synthesis tools don't handle well the case of there being zero gates in the design, as that means there's zero die area needed before routing. I'm guessing the tool is hitting some internal divide-by-0.

So yes, you can simply connect a wire to an output. That by itself is perfectly valid. And you can even connect an input directly to an output. As long as you have any other gates in the design, even unrelated/unconnected to the ports/nets in your example, the synthesizer would be happy, as there'd be non-zero die area.

So I bet this would work fine:

module and_gate (
    input   [1:0]   io_button,
    output  [2:0]   io_led
);

wire wire1;
assign wire1 = io_button[0];
assign io_led[0] = wire1;

assign io_led[1] = ~io_button[1];  // added line, just to infer a gate somewhere

endmodule