Want to use 1 Verilog module output for 2 inputs

Everything in my project works perfectly. Basically I use a 2to1mux to determine which of two 7-bit inputs gets displayed on a hex display and 7 LEDs. It works perfectly, but I was wondering how I can use the one 7-bit output from my module for both the LEDs and the Hex display?

Here is my main file:

module Majority(SW, LEDR, KEY, HEX0);

    input [16:0] SW;
    
     input [3:3] KEY;
    output [6:0] LEDR;
     output [6:0] HEX0;
    
    my21mux m21m_inst(.sel(KEY[3]), .in0(SW[6:0]), .in1(SW[16:10]), .y(HEX0[6:0]));

endmodule





module my21mux(sel, in0, in1, y);
input sel, in0, in1;
output y;

wire nsel;
wire t1;
wire t2;



not n(nsel, sel);

and a1(t0, in0, sel);
and a2(t1, in1, nsel);

or o(y, t1, t2);

// y should determine which set of switches to display on the LEDs / Hex


endmodule

And here is my test bench:

`timescale 1 ns/1 ns

module TestBench();
 //stimulus connections   
    reg [3:3] KEY;
    reg [16:0] SW;
    wire [6:0] LEDR;
    wire [6:0] HEX0;
   my21mux S(KEY, SW[6:0], SW[16:10], HEX0[6:0]);
// Test Procedure
    initial begin
KEY[3]=0;SW[10]=0;SW[0]=0; #5;
KEY[3]=0;SW[10]=0;SW[0]=1; #5;
KEY[3]=0;SW[10]=1;SW[0]=0; #5;
KEY[3]=0;SW[10]=1;SW[0]=1; #5;
KEY[3]=1;SW[10]=0;SW[0]=0; #5;
KEY[3]=1;SW[10]=0;SW[0]=1; #5;
KEY[3]=1;SW[10]=1;SW[0]=0; #5;
KEY[3]=1;SW[10]=1;SW[0]=1; #5;
end
endmodule

Any ideas would be appreciated, thank you!

Solution

It is not clear how your main_file is structured, since there is an unmatched endmodule keyword that suggests that you wanted to create some sort of wrapper to your my21mux module. Probably that module is not used anyway since in TestBench you instantiate my21mux mux anyway.

Quick and dirty solution, 2 muxes:

  my21mux S_hex0(KEY, SW[6:0], SW[16:10], HEX0[6:0]);
  my21mux S_ledr(KEY, SW[6:0], SW[16:10], LEDR[6:0]);

With only one mux instance that has one output, which is assigned to both your signals:

  wire [6:0] mux_out;
  my21mux S_hex0(KEY, SW[6:0], SW[16:10], mux_out);
  assign HEX0 = mux_out;
  assign LEDR = mux_out;

In my opinion the following would be easier, with no need of a custom defined mux:

  wire [6:0] mux_out = KEY ? SW[6:0] : SW[16:10]; //ternary operator
  assign HEX0 = mux_out;
  assign LEDR = mux_out;

Please check out ternary operator usage.

Also, in your my21mux you associate in0 AND sel and in1 AND nsel, while the name obviously suggests that it should be the other way round.