How to get more info in testbench results?

Question

I realize that this may be very easy to fix but I can't find a way to make it work. My question is how can I get visual signals of CE2 and CEO in this case? I know by looking on RTL Scheme CE2 and CEO isn't connected to pins. And I just can't connect them. CE2 should be ON when first counter reach 9 but on waveform its always as X. And CEO should be ON when Q is 9 but on waveform its always Z. This circuit is just for self learning.

Testbench

Circuit Scheme

TOP MODULE:

`timescale 1ns / 1ps

module top(
 input             CLK,
  input             CLR,
  input             CE,
  input             CE2,
  output reg [3:0]  Q,
  output reg [3:0]  Q2,
  output  wire      CEO,
  output            CEO2
);
wire CLK;
wire CLR;
wire CENABLE;
wire  CE2;
wire Q;
wire Q2;
wire CEO;
wire CEO2;


licznik licznik(.CLK(CLK),.CLR(CLR),.CE(CE),.CEO(CENABLE),.Q(Q));
licznik2 licznik2(.CLK(CLK),.CLR(CLR),.CE2(CENABLE),.Q2(Q2),.CEO2(CEO2));

endmodule

TESTBENCH:

`timescale 1ns / 1ps

module testbench;
reg CLK;
reg CLR;
reg CE;
reg CE2;
wire [3:0]   Q;
wire [3:0]   Q2;
wire CEO;
wire CEO2;

top UUT (
.CLK(CLK),
.CLR(CLR),
.CE(CE),
.CE2(CE2),
.Q(Q),
.Q2(Q2),
.CEO(CEO),
.CEO2(CEO2)
);

initial CLK=1'b0;
always #5 CLK=~CLK;
initial
begin
    CLR = 1'b1;
    CE= 1'b1;
    #18 CLR = 1'b0;
end
endmodule

FIRST MODULE:

 `timescale 1ns / 1ps
     module licznik(
         input             CLK,
          input             CLR,
          input             CE,
          output reg [3:0]  Q,
          output            CEO
        );
        
        always @(posedge CLK or posedge CLR)
          if(CLR)
            Q <= 4'd0;
          else begin
            if(CE) begin
              if(Q != 4'd9)
                Q <= Q + 1;
              else
                Q <= 4'd0;
            end
          end
        
        assign CEO = CE & (Q == 4'd9);
        endmodule

SECOND MODULE:

`timescale 1ns / 1ps

module licznik2(
 input             CLK,
  input             CLR,
  input             CE2,
  output reg [3:0]  Q2,
  output            CEO2
);

always @(posedge CLK or posedge CLR)
  if(CLR)
    Q2 <= 4'd0;
  else begin
    if(CE2) begin
      if(Q2 != 4'd9)
        Q2 <= Q2 + 1;
      else
        Q2 <= 4'd0;
    end
  end

assign CEO2 = CE2 & (Q2 == 4'd9);
endmodule

Answer 1

I ran your code on 2 simulators, and I got compile errors on both. Try your code on EDAPlayground.

To fix the compile errors, I removed the wire declarations in module top. To fix the problem with Z on CEO, I replaced CENABLE with CEO. Here is the new top module:

module top(
 input             CLK,
  input             CLR,
  input             CE,
  input             CE2,
  output reg [3:0]  Q,
  output reg [3:0]  Q2,
  output  wire      CEO,
  output            CEO2
);

licznik licznik(.CLK(CLK),.CLR(CLR),.CE(CE),.CEO(CEO),.Q(Q));
licznik2 licznik2(.CLK(CLK),.CLR(CLR),.CE2(CEO),.Q2(Q2),.CEO2(CEO2));

endmodule

CE2 is X because it is an undriven input. I think you can just delete it.