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verilogfpga

Verilog: Cross module reference for pure functions

Are pure (only accessing input regs) functions synthesizable when they are accessed as a cross module reference?

Example:

// a module with functions inside
module functions;
  function fn1;
  input reg i;
    fn1 = i;
  endfunction
endmodule

// must be synthesizable vvv 
module consumer(input i, output o);
   functions fns();
   assign o = fns.fn1(i);
endmodule
Solution

  • It's perfectly synthesizable because a pure function gets in-lined into the combinatorial logic inside the the calling module. There are no cross-module reference to any signals after that. But many synthesis tools haven chosen not to handle any kind of cross-module reference, even if the hierarchy gets flattened.

    In SystemVerilog you would define a function inside a package and then import the package into your module. Any synthesis tools that supports the most basic SystemVerilog constructs also supports this.