Synth 8-27 Primitives not Supported in Vivado

Question

I am running the synthesis for my chip design code (Verilog) in Vivado. The behavioral simulation worked fine. But, during synthesis, it returns the following error:

**[Synth 8-27] - primitive not supported** 

This is the code where Vivado throws this error:

primitive VIS_mux (q, d0, d1, s);
   output q;
   input s, d0, d1;
   
`protect
   table
   // d0  d1  s   : q
      0   ?   0   : 0 ;
      1   ?   0   : 1 ;
      ?   0   1   : 0 ;
      ?   1   1   : 1 ;
      0   0   x   : 0 ;
      1   1   x   : 1 ;
   endtable
`endprotect

endprimitive

I would appreciate if anyone could please help to resolve this issue.

How can I convert the primitive to a module?

Answer 1

The error means that you can not use the primitive keyword for synthesis with this tool. As you surmised, you can use a module instead.

The standard way to code a synthesizable multiplexer is to use the conditional operator. Here is a module version:

module VIS_mux (q, d0, d1, s);
   output q;
   input s, d0, d1;
   assign q = (s) ? d1 : d0;
endmodule