Is there a simple way to tell the difference in how this code would be synthesized and implemented

Question

would these two snippets synthesize the same way? (I realize they need to be in an always block and have declarations for the registers used). I am also thinking this would vary by the synthesis tool used. Vivado might produce one result and Quartus another. Is there an easy way to check if this is the case. Will https://www.edaplayground.com/ be a meaningful way to test this?

if (some_condition) begin
   if(another_condition) begin
      output <= 1'b1;
   end else begin
      output <= output;
   end
end else begin
   if(another_condition) begin
      output <= 1'b1;
   end else begin
      output <= 1'b0;
   end
end

if (another_condition) begin
   output <= 1'b1;
end else begin
   if (some_condition) begin
      output <= output;
   end else begin
      output <= 1'b0;
   end
end

Answer 1

If you are interested in FPGA, and you have a thee input LUT, the way to go will be to take this logic and write to a single LUT.

If the tool follows a greedy strategy to merge LUTs with free inputs it will end up having a single LUT.