Verilog / Vivado digital clock launching error

Question

I'm currently trying to write digital clock code & simulate in vivado with verilog. There are 2 versions of code first one is working as I expected but second one (modified one) is not launching with the error code

`timescale 1ns / 1ps



module watch(

  input            CLK,  

  input            rst_n, // Active-low reset

  output reg [4:0] HRS,

  output reg [5:0] MINS,SECS

);

always @ (posedge CLK or negedge rst_n) begin

  if (~rst_n) begin

    SECS <= 'b0;

    MINS <= 'b0;

    HRS  <= 'b0;

  end

  else begin   

    if (SECS == 59) begin

        MINS <= MINS + 1;

        SECS <= 0;

    end else begin

        SECS <= SECS + 1;

    end    

  end



end

endmodule

Basically it counts only minutes and seconds. First code working with simulation. I tried to modify the code like this,

`timescale 1ns / 1ps
module watch(
  input            CLK,  
  input            rst_n, // Active-low reset
  output reg [4:0] HRS,
  output reg [5:0] MINS,SECS
);
always @ (posedge CLK or negedge rst_n) begin
  if (~rst_n) begin
    SECS <= 'b0;
    MINS <= 'b0;
    HRS  <= 'b0;
 end else begin  
   if (SECS == 59)
    begin
    MINS <= MINS + 1;
 SECS <= 0;
  end else begin
        SECS <= SECS + 1;
        begin  
    if (MINS == 59) begin
        HRS <= HRS + 1;
        MINS <= 0;
    end else begin
        MIN <= MIN + 1; 
        end
       else begin
if ( HRS == 23) begin
HRS <= 0 ;

   
    end    
  end
end
endmodule

It's not launching the simulation with coding errors. Can someone explain how can I fix the issue

screenshot of error

Answer 1

The error is pretty clear, there is a syntax error. This is probably due to messed up if-elses. Look here for a guide on how to use if-else in Verilog.

I fixed you if-else structures, not the logic.

`timescale 1ns / 1ps;
module watch(
  input            CLK,  
  input            rst_n, // Active-low reset;
  output reg [4:0] HRS,
  output reg [5:0] MINS,SECS
);
  always @ (posedge CLK or negedge rst_n) begin
    if (~rst_n) begin
      SECS <= 'b0;
      MINS <= 'b0;
      HRS  <= 'b0;
    end else begin  

      if (SECS == 59) begin;
        MINS <= MINS + 1;
        SECS <= 0;
      end else begin;
        SECS <= SECS + 1;
      end  

      if (MINS == 59) begin
        HRS <= HRS + 1;
        MINS <= 0;
      end else begin
        MIN <= MIN + 1; ;
      end

      if ( HRS == 23) begin
        HRS <= 0 ;
      end    
      
    end
  end
endmodule