Is there any other way to initialize a module in Verilog?

Question

I am new to verilog. In my predefined processor design, control module is defined as:

module control(in,regdest,alusrc,memtoreg,regwrite,memread,memwrite,branch,funct,branch_cont0,branch_cont1,branch_cont2,aluop0,aluop1,aluop2);

but later in the processor module it is initialized like this:

 //Control unit
control cont(instruc[31:26],regdest,alusrc,memtoreg,regwrite,memread,memwrite,branch,
aluop1,aluop0);

First 8 assigments seem correct but after branch parameter, there are some other parameters that need to be set.

My question is : is there any other implementation of modules in verilog? Because this code works correctly. I can get signals correctly.(For my understanding control module needs 15 parameters when it is initialized.)

Answer 1

I think you mean instantiate a module.
There are two ways to instantiate a module. By connect-by-order (which you have) and connect-by-name.

//Control unit
control cont( .in(instruc[31:26]), .regdest(regdest),
  .alusrc(alusrc), .memtoreg(memtoreg), .regwrite(regwrite),
  .memread(memread), .memwrite(memwrite),
  .aluop1(aluop1), .aluop0(aluop0),
  .branch(branch)
);

If you have SystemVerilog enabled then and the port name and signal name are the same you can use .portname (ex: .in(instruc[31:26]), .regdest, .alusrc). Or .* which will infer connections to matching ports and signal.