Search code examples
system-verilogverification

Clocking block input signal can not be driven

Clocking block input signal data_rvalid_i can not be driven.

CB_CODE:

  default clocking response_driver_cb @(posedge clk);    

    input   reset;               
    output  data_req_o;
    input   data_gnt_i;
    output  data_addr_o;
    output  data_we_o;
    output  data_be_o;
    input   data_rvalid_i;
    output  data_wdata_o;
    input   data_rdata_i;
    input   data_err_i;    
  endclocking

Driver Patch Code:

  task reset_signals();

    `DRIVER_IF.data_rvalid_i  <= 1'b0;
    `DRIVER_IF.data_gnt_i     <= 1'b0;
    `DRIVER_IF.data_rdata_i   <= 'b0;
    `DRIVER_IF.data_err_i     <= 1'b0;
  endtask : reset_signals
Solution

  • Clocking block inputs are read-only; You cannot drive them.

    Ether remove the driving statement, or change the clocking block direction of that signal to output ot inout.