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variable-assignmentsystem-verilog

(VERI-1322) prefix of assignment pattern must be a data type

Here is a snippet from my code;

always_ff @(posedge clk) begin : output_assigment // left side should only be "_q"
    if(reset_n == 1'b0 || clear == 1'b1) out_signal_q <= {8'{!(REPORT_POL)}};

But i see this error: (VERI-1322) prefix of assignment pattern must be a data type

How can this be corrected for the assignment "out_signal_q <= {8'{!(REPORT_POL)}}" Can you please help ? end

Solution

  • It always helps to show declarations of all signals involved in the expression. I have to assume that REPORT_POL is a single bit and you want it replicated 8 times to assigned to out_signal_q. In that case you want to remove the ' and just write

    out_signal_q <= {8{!REPORT_POL}};