I'm trying to implement some logic that is either triggered on a rising or falling edge of the same clock, depending on a clock polarity signal. I tried the following but got an error message in Quartus 15.1 (error id: 10628): "Can't implement register for two clock edges combined with a binary operator".
process(clk)
begin
if (rising_edge(clk) and pol='0') or (falling_edge(clk) and pol='1') then
-- logic
end if;
end process;
My current workaround is to just write the whole logic block twice, once with each condition separately. But since the logic block isn't that small and still under development this really isn't optimal. Does anyone have a better solution to this?
Edit: One easy way to achieve this would be a gated clock, but from what I understand, this is generally a bad idea, so I tried to do it without a mux or xor in the clock path.
Edit: I misunderstood the question. The below only applies if pol is a constant:
Try the oldschool way of writing this, with separate event attribute and level:
if clk'event and clk = pol then
-- logic
end if;
If pol is '1', this synthesises to the same thing as rising_edge(clk).