Designing T-Flipflop on Quartus

Question

I'm new to VHDL, and I wanna design a T Flip-Flip that toggles and change Q based on T input, and here is what I have

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity T_flipflop is

   Port ( T : in std_logic;
         CLK : in std_logic;
         Q : out std_logic ); 

end T_flipflop;


architecture Behavioral of T_flipflop is
 begin
  process (CLK) 
  --- The error in the following line
    if (CLK’event and CLK = ‘1’ )then
        Q <= Q when T = '0';
       Q <= not Q when T = '1';
    end if;
end process;
end Behavioral;

But every time I run it on Quartus, I get the following errors, what am I doing wrong? Thanks in advance

Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
    Info: Processing started: Sun Dec 05 19:20:03 2021
    Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
    Info: Processing started: Sun Dec 05 19:20:03 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off T_FlipFlop2 -c T_FlipFlop2
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
Error (10500): VHDL syntax error at T_FlipFlop2.vhd(19) near text "if";  expecting "begin", or a declaration statement
Error (10500): VHDL syntax error at T_FlipFlop2.vhd(19) near text 
Error (10500): VHDL syntax error at T_FlipFlop2.vhd(19) near text 
Error (10500): VHDL syntax error at T_FlipFlop2.vhd(19) near text 
Info (12021): Found 0 design units, including 0 entities, in source file t_flipflop2.vhd
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 4 errors, 1 warning
    Error: Peak virtual memory: 4836 megabytes
    Error: Processing ended: Sun Dec 05 19:20:11 2021
    Error: Elapsed time: 00:00:08
    Error: Total CPU time (on all processors): 00:00:18
    Error: Peak virtual memory: 4836 megabytes
    Error: Processing ended: Sun Dec 05 19:20:11 2021
    Error: Elapsed time: 00:00:08
    Error: Total CPU time (on all processors): 00:00:18
Error (293001): Quartus Prime Full Compilation was unsuccessful. 6 errors, 1 warning

Answer 1

process (CLK) needs an is begin.

Change line 19 to:

process (CLK) is begin

Here is a reference for more info: https://fpgatutorial.com/using-vhdl-process-blocks-to-model-sequential-logic/