I have used two different modules in generate loop statement both are inter dependent. so, I want to know to how to execute them sequentially.
Verilog describes behavior of hardware. The hardware is a set of connected devices which all function in parallel. However, connections guarantee that eventually (takes some time) outputs of devices will propagate to the inputs of driven devices which outputs will be updated accordingly, and which will drive their fanout devices.
Verilog simulates this behavior by using event-driven simulation. If an output of a device changes, it will evaluate (or re-evaluate) the devices driven by this output.
Synthesis generates those connected hardware devices from verilog description.
So, no matter in which order you instantiate your modules, the order of evaluation is only defined by their connections. It does not matter if modules are in generate blocks or not. Just make sure that they are connected correctly.