How do I generate an I²C clock with these specs?

I2C clock specifications the clock from fpga is 100MHz and I need to run it at 400kHz, so in order to make 400kHz clock, I divided 100MHz/(2^8)=390625(close to 400kHz)(please tell me a more optimal way for clock dividers) here 8 is the no. of bits, so I made a counter(8 downto 0) and took its 8th(index) bit as my clock for the i2c communication process(vhdl). please guide me as to how I can generate the required clock. thank you

signal count:std_logic_vector(8 downto 0);
signal sign:std_logic;
process(clk,rst)
begin
 if rst='1' then
 count<=(others=>'0');
 elsif rising_edge(clk) and rst='0' then 
 count<=count+1;
 end if;
 sign<=count(8);
end process;

Solution

You can just divide the clk by 250 to get a 400kHz clk. Something along the lines of:

signal count : integer range 0 to 250;
signal clk400 : std_logic; 
process (clk100, rst)
begin 
    if rst ='1' then 
        count  <= 0;
        clk400 <= '0'; 
    elsif rising_edge(clk100) then
       count <= count +1;
       if count = 249 then 
           count  <= 0;
           clk400 <= not clk400;
       end if;
    end if;
end process;

Or, depending on you FPGA and tools, you could use a PLL.