Error (10448): VHDL error at teste.vhd(33): record type std_ulogic is used but not declared

Question

I was trying to do a work and this error is boring me, i pass to a new project teste.vhdl and this keep happening, i need to have two barriers of clock one for input and another to output, to use timequest with combinational logic. The 'and' is just a example.

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

ENTITY teste IS
PORT(
    clock :     in std_logic;
    clear :     in std_logic;
    a       :   in std_logic_vector(3 downto 0);
    b       :   in std_logic_vector(3 downto 0);
    s       :   out std_logic_vector(3 downto 0)
);
END teste;

ARCHITECTURE comportamento OF teste IS
signal a1,b1,s1 : std_logic_vector(3 downto 0);
begin

FF_in: process(clock.clear)
 begin
    if clear = '1' then
        a1 <= "0000";
        b1 <= "0000";
    elsif clock'event and clock = '1' then
        a1 <= a;
        b1 <= b;
    end if;
end process;
    
    s1 <= a1 and b1;
    
FF_out: process(clock.clear)
 begin
    if clear = '1' then
        s <= "0000";
    elsif clock'event and clock = '1' then
        s <= s1;
    end if;
end process;
    
END comportamento;

Answer 1

You have used a . Rather than , in the process sensitivity list. Using a . Is trying to access a record field.