Verilog error "continuous assignment output must be a net"

Question

I am working on a an assignment where I have to synthesize my Verilog code. I wrote the code and compiled and simulated, and everything worked fine. When I went to synthesize, the design compiler gave me an error in one of my modules. This module represents a simple 8-bit shift register with a data buffer. When I synthesize, it gives me an error:

continuous assignment output buffer must be a net

I don't know what this message is stating.

module shiftReg(output shift_out,
output reg [7:0] data_buff,
input shift_write, clk, shift_in,
input [7:0] data);

    reg [7:0] buffer;
    assign shift_out = buffer[7];
    assign buffer[0] = shift_in; //This is where it states an error.
    always@(posedge clk) begin
        if(shift_write == 1) begin
            buffer <= {buffer[6:0],shift_in};
        end
    end
    always@(shift_write) begin
        if(shift_write == 0) begin
            data_buff <= buffer;
            buffer <= data;
        end
    end

endmodule 

Answer 1

The message is telling you that the signal you are assigning to with the continuous assignment (using the assign keyword) must be a net type variable, such as a wire. But, you declared buffer as a reg type variable. This is illegal, and your simulator should have at least warned you about this before you got to synthesis. The simulators I use gave me compile errors.

You can simply delete this line:

assign buffer[0] = shift_in; //This is where it states an error.

Inside the 1st always block, you already assign buffer[0] to shift_in implicitly in the line:

        buffer <= {buffer[6:0],shift_in};

---

After you fix that, you still have a problem. The 2nd always block is odd for a number of reasons. The syntax is legal, but it does not adhere to good synthesis coding practices. Perhaps you meant to combine the 2 always blocks into 1:

module shiftReg (
    output shift_out,
    output reg [7:0] data_buff,
    input shift_write, clk, shift_in,
    input [7:0] data
);

    reg [7:0] buffer;
    assign shift_out = buffer[7];
    always @(posedge clk) begin
        if (shift_write) begin
            buffer <= {buffer[6:0], shift_in};
        end else begin
            data_buff <= buffer;
            buffer <= data;
        end
    end
endmodule