I'm trying to build a little game in VHDL and, therefore, I need to use two matrices of std_logic elements. Here is how I initialized my two matrices :
type matrix_type is array (0 to 7) of std_logic_vector(7 downto 0);
shared variable matrix : matrix_type := (
others => (others => '0')
);
shared variable frozen : matrix_type := (
others => (others => '0')
);
But this takes A HUGE amount of blocks of logic cell to be done. Without doing this, I am only using 75/160 logic elements, while when I am doing this, I'm using 207/160 logic elements! Quartus can't even compile this code because of the amount of logic elements that are used.
Why is this so? How is that possible that initializing such matrices needs so many logic elements? Do you have a solution to use less of them, or to initialize them another way?
Thank you!
Because probably you are using slices of the fpga to store the initial value. The best way to do store values on a fpga is use a block ram. You can infer it with vhdl code or create the memory with the fpga vendor tool and connect it.