started with verilog and trying to understand what is happening in this piece of code of module instantiation

Question

clock #(.N(N))  //-- N parameter
Pres1(
.CLK(clk),
.O_SPI_CLK(clk_out) );

what i don't understand is #(.N(N) and use of pres1();

Answer 1

Verilog uses modules to define a group of devices in a hierarchical manner. Module instances define a hardware device. Every module instance has a name.

   moddedf modinst(params);

where moddef is the namd of the module definition (similar to a function of procedure in a generic programming languate). 'modinst' is the name of the instance of the module (not commonly found in generic programming languages). Instances are used to express hierarchy of hardware designs.

so, in your case

clock Pres1(...);

module 'clock' is instatntiated with instance name 'Pres1'.

Instance parameters (defined within a module definition) represent connections between hardware devices (module instance).

clock Pres1(.CLK(clk),.O_SPI_CLK(clk_out) );

in the above, port CLK of module 'clock' is connected to a wire 'clk' and port O_SPI_CLK is connected tot he wire clk_out. Types of the ports (net, variabel) are supposed to be defined within the module definition, and type of the signals connected to it in the module which instantiates the module 'clock' (a parent module).

Apparently, module 'clock' also uses parameter N. Parameter is similar to a constant in a generic language. Parameter N is also defined in the parent module.

clock#(.N(N1)) Pres1(.CLK(clk),.O_SPI_CLK(clk_out) );

In the above a value of the parameter(constant) N1 defined in the parent module is assigned to the parameter N int the module 'clock'. I intentionally changed N to N1 to make it a bit more clear. There is no need to change it otherwise.

so,

clock#(.N(N)) Pres1(.CLK(clk),.O_SPI_CLK(clk_out) );

instantiates module clock as an instance Pres1, connects its CLK and O_SPI_CLK ports to signals clk and clk_out and passes parameter N to the parameter N of the module.