sva event scheduling with $display/uvm_error

Question

So I recall when an assertion triggers the data signals in the assertion are from just prior to the clock edge.

I'd like to put a helpful error message in my assertion to let the user know what went wrong, but by the time $display() happens the data has already changed.

As an example the below assertion will fail whenever data=0 when a ready/valid handshake occurs. However the $display that is printed will show data=1 if there is coincidentally a rising edge of data when the assertion fired.

  default clocking CLK @(posedge clk);
  endclocking
  //Assertion triggers an error if data is not = 1 when new data is clocked into the DUT.
  POS_DATA: assert property ((ready & valid) |-> data) else $display("[%t] POS_DATA fail data:%d",$time,data);

Is there a better way to code this assertion?

Created an EDAPlayground Example and looks like all the simulators do the same thing, so seems like it's my fault.

Answer 1

All you need to do is add $sampled(data)

POS_DATA: assert property ((ready & valid) |-> data) else $error(" POS_DATA fail data:%d",$sampled(data));

And you should be using $error instead of $display. You'll thank me later when you start running regressions and getting coverage reports.