I just learned about memory management and I am currently trying to figure out what Page Table is. Per my understanding, Page Table is a data structure that works just like hash tables, used to map and connect both logical and physical memory address in an Operating System.
We will need one register to determine the location of a page table of a process. But how many registers do we need to determine the location of a multilevel page table, for example a two and three level page table? How do you determine it?
Also, how will cache (L1-L3) in the processor affect memory reference access to page table? Will the majorities miss or hit? Why does it happen?
I tried to find references for this, but it leads me to TLB and I haven't learned about it yet. Might say that I am really beginner in OS. Help :)
Based on Nate's answer, we only need one register at the top level of the table, and the entries in the table are pointers to the next levels so there won't be any needs of more than one register in any level of page table.