Verilog - Changing a reg in sensitivity list in Always block

Question

reg A,B,C;
always @(*)begin
//some other computations
C=B;
//some other computations
A=C;
end

always @(posedge clk)begin
B<=A;
end

Hi there,

In the code above, at the posedge of clk reg A changes the value of reg B and that starts the process of first always block since B is in the sensitivity list. My question is what will be happening at the line "C=B" since reg C is also in the sensitivity list? Will that start the process of the first loop again and causes an infinite loop?

I check that on simulation and it works fine. But I don't know want would happen on hardware.

My guess is it will not cause a problem. Since Verilog only creates a LUT to mimic the algorithm inside of the always block, that will not cause a problem on hardware. However, I am not sure so I would like to ask.

Thank you,

Answer 1

Remember that procedural code executes one statement at a time. Your code is effectively interpreted the same as

initial begin
       @(B or C) // wait for a change on B or C
       C = B;
       A = C;
       @(B or C) // wait for a change on B or C
       C = B;
       A = C;
       @(B or C) // wait for a change on B or C
       C = B;
       A = C;
       ...
       end

The assignment to C happens, but any change to C has already happened before you get to the next @. Synthesis interprets C as an intermediate value.