Afaik, in x86 all that operating system done is to set CR3 register and let MMU do the left to transform linear addr to physical addr. But since this work is done by MMU, then the MMU should know the rule that how multi-level page table is divided. However I've never seen any documents talking about such detail. Is there anything that I misunderstood?
The page-table format is part of the ISA that hardware (including the page-walker(s) built-in to each CPU core) implements, and which software should therefore follow.
So page-walk hardware in an x86 CPU is just built to chop up addresses the x86 way. You can look at the ISA documentation describing the page table format as documenting what the hardware will be looking for.
When there's a choice in page-table formats (like PAE 9 bits per level or legacy 32-bit 10 bits per level, or x86-64 PML5 5-level page tables for 57 virtual bits vs. standard PML4), the choice is set by a control register.
"The MMU" isn't really a separate thing in x86 (or other modern CPUs); it's part of a CPU core and can be affected by control-register bits. If it was a fully separate chip, you might set a top-level page directory with an out instruction or a store to a special MMIO address, instead of mov to cr3.