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system-verilogassertassertion

SV Assertion: Check Signal is High for a particular State and does not change during that State

I want to check If my Signal A is high as long as I am in the FSM 'FSM_WAIT' State. If A goes low anywhere in this State I should flag an error. The Assertion should check that A goes High during the state and stays High throughout.

I tried a sample Code somewhat like this.

        @(posedge clk )
        disable iff (!reset)
        (fsm_state==  FSM_WAIT ) && A |-> ##Duration A;
    endproperty : p_try  

Doesn't see correct to me though, please help. Thanks
Solution 
  • (fsm_state==FSM_WAIT ) && A |-> A until (fsm_state!=FSM_WAIT )