Improper array length of a 5-bit input rom on VHDL code

Question

I am trying to create a 5-bit input 32-bit output rom but on testbench section I get an error which says the following:

COMP96 ERROR COMP96_0367: "Improper array length (8). Expected length is 5." "testbench.vhd" 18 26
COMP96 ERROR COMP96_0367: "Improper array length (8). Expected length is 5." "testbench.vhd" 17 26
COMP96 ERROR COMP96_0367: "Improper array length (8). Expected length is 5." "testbench.vhd" 16 14
COMP96 ERROR COMP96_0367: "Improper array length (4). Expected length is 5." "testbench.vhd" 15 26

And the testbench code is the following:

library IEEE;
use IEEE.std_logic_1164.all;

entity rom_test is
end entity rom_test;

architecture dataflow of rom_test is
    signal input_address: std_logic_vector (4 downto 0);
    signal output_data: std_logic_vector (31 downto 0);
    
begin
    g1: entity work.rom(dataflow)
        port map(addr=>input_address, data_out=>output_data);
        
        input_address <= x"0",
                         x"01" after 20 ns,
                         x"02" after 40 ns,
                         x"03" after 60 ns;
end architecture dataflow;

Can someone help?

Answer 1

input_address is a std_logic_vector of length 5 (4 downto 0). You are trying to assign it a one or two digit hexadecimal value, which is of length 4 and 8.

One way to to fix it is to concatenate a 0 to a one digit hex number, resulting in a vector of length 5:

input_address <= '0' & x"0",
                         '0' & x"1" after 20 ns,
                         '0' & x"2" after 40 ns,
                         '0' & x"3" after 60 ns;

Another way is to only assign the 4 lowest bits of input_address:

input_address(4) <= '0';
input_address(3 downto 0) <= x"0",
                             x"1" after 20 ns,
                             x"2" after 40 ns,
                             x"3" after 60 ns;