Verilog compiler errors in Modelsim when simulating register file

Question

I'm trying to write some verilog code to create a register file containing 32 32-bit registers.

Register File Input/Output

Here is my code below:

module regfile (clk, we, ra1, ra2, wa, wd, rd1, rd2);

    
    input  logic        we, 
    input  logic        clk, 
    input  logic [4:0]  ra1, ra2, wa, 
    input  logic [31:0] wd, 
    output logic [31:0] rd1, rd2;

    logic [31:0]     rf[31:0];

    always @ (posedge clock) 
        begin
            rd1 = rf[ra1];
            rd2 = rf[ra2];
        end  
  
    always_comb
        begin
            if(we == 1)
                rf[wa] = wd;
                
            rf[0] = 0;
        end

endmodule

I modeled the code above based on some tutorial files, so I am very confused why Modelsim gives compilation errors.

Are there any obvious mistakes with the syntax?

When running the command in the CMD: vsim -do regfile.do

How can I get it to output the verbose warnings so I can actually see what is causing the problem?

Answer 1

You are using a bizarre combination of pre-2001 and post-2001 syntax. I recommend post-2001 syntax for your ports:

module regfile (
    input  logic        we, 
    input  logic        clk, 
    input  logic [4:0]  ra1, ra2, wa, 
    input  logic [31:0] wd, 
    output logic [31:0] rd1, rd2
    );