Verilog wire to register

Question

I have a bidirectional bus and I can read the inputs from it into wires, but I have a hard time do logic with them and assign them back on the BUS as an output, or connecting them into registers so I could work with the values.

All help and response is appreciated.

Jozsó

Answer 1

There are two basic classes of variables in verilog: nets and regs. reg is used to do calculations in procedural blocks, nets are used to connect different entities such as module instances or UDPs.

So, they have different functions and different rules and operators. So, wires are connected through module instance ports and/or a continuous assign operators, which ideally represent wire connections.

The basic rule are

1. a net value can be used as a rhs of a register expression. So, it can be assigned to a register within a procedural (e.g. always) block.
2. a reg value can be assign to a net in a continuous assign operator, or in an output port connection.
3. net cannot be assigned any value within an always block
4. reg cannot be assigned with a continuous assignment

The basic scheme to work around it is the following:

wire --> always block ( reg ) --> assign (wire)

Here is an example:

module top (bus, en);
   inout wire bus;
   input wire en;
    
   reg tmp;
  
   always @*
     tmp = bus;

  assign bus = en ? tmp : 1'bz;

endmodule