How combine multiple VHDL codes to make one system

Question

I have multiple VHDL code coming from separate sources, and I want to combine them to make a single system.

My understanding is that I have to extract entities and architectures that I'm interested in from each code then I make a new entity that combines them and same for architecture.

I'm missing the next steps in how to use these in the process.

It would be nice to get some tips and tricks from you guys on how to do it correctly and avoid the mistakes that a newbie in VHDL like me will probably do.

The figure summarizes what I have and what I need.

Multiple VHDL to one

Regards

Answer 1

The example can be if you have two modules, the mdl_sub sub-module:

library ieee;
use ieee.std_logic_1164.all;

entity mdl_sub is
  generic(
    A_L : natural;
    Z_L : natural);
  port(
    clk_i : in  std_logic;
    rst_i : in  std_logic;
    a_i   : in  std_logic_vector(A_L - 1 downto 0);
    z_o   : out std_logic_vector(Z_L - 1 downto 0));
end entity;


library ieee;
use ieee.numeric_std.all;

architecture syn of mdl_sub is
  signal z : std_logic_vector(z_o'range);
begin

  process (clk_i, rst_i) is
  begin
    -- Clock
    if rising_edge(clk_i) then
      z <= std_logic_vector(unsigned(z) + unsigned(a_i));
    end if;
    -- Reset
    if rst_i = '1' then
      z <= (others => '0');
    end if;
  end process;

  -- Drive output
  z_o <= z;

end architecture;

and the mdl_top top-module:

library ieee;
use ieee.std_logic_1164.all;

entity mdl_top is
  generic(
    M0_A_L : natural := 8;
    M0_Z_L : natural := 8;
    M1_A_L : natural := 4;
    M1_Z_L : natural := 4);
  port(
    clk_i  : in  std_logic;
    rst_i  : in  std_logic;
    m0_a_i : in  std_logic_vector(M0_A_L - 1 downto 0);
    m0_z_o : out std_logic_vector(M0_Z_L - 1 downto 0);
    m1_a_i : in  std_logic_vector(M1_A_L - 1 downto 0);
    m1_z_o : out std_logic_vector(M1_Z_L - 1 downto 0));
end entity;


library ieee;
use ieee.numeric_std.all;

architecture syn of mdl_top is
begin

  -- Sub-module 0
  mdl_sub_0 : entity work.mdl_sub
    generic map(
      A_L => M0_A_L,
      Z_L => M0_Z_L)
    port map(
      clk_i => clk_i,
      rst_i => rst_i,
      a_i   => m0_a_i,
      z_o   => m0_z_o);

  -- Sub-module 1
  mdl_sub_1 : entity work.mdl_sub
    generic map(
      A_L => M1_A_L,
      Z_L => M1_Z_L)
    port map(
      clk_i => clk_i,
      rst_i => rst_i,
      a_i   => m1_a_i,
      z_o   => m1_z_o);

end architecture;

then the two files with the modules can be compiled separately, and the mdl_sub is then integrated into mdl_top, as Brian Drummond describes.

Sorry for the longer modules, but I had those readily available as examples ;-)