Passing objects into SystemVerilog tasks/functions - Vivado Zynq Verification IP / API

Question

I have a testbench in Vivado which has a hierarchy of IP--some custom IP and some Xilinx IP, like the Zynq Processing System. The Zynq Processing System also has an associated Verification IP library that has useful API for doing things like loading DDR.

I would like to write a task which leverages the Zynq Verification IP (and associated API) inside it. I can't figure out how I would implement this in my testbench? I am new to SV, and am guessing that I need to pass the zynq processing system object as an argument so I can access it's API inside my super-task.

Updated example of what I'm trying to do in my testbench. I realize this isn't proper SystemVerilog, it's just to demonstrate the functionality I'm trying to obtain. TOP is a module defined in some other .sv file that contains the definition of a task called T:

module tb();

  TOP TIPTOP(), TIPITTYTOP();

  task myTask(input TOP T);
    begin
        T.T;
    end
  endtask
  
initial begin
  
  myTask(TIPTOP);
  myTask(TIPITTYTOP);
  
end
  
endmodule

Answer 1

Another answer to the updated question

This can only be done if the module TOP is not a module but a different flavour of module, called an interface. There is a special kind of SystemVerilog variable called a virtual interface which is a variable that can store a reference to the instance of an interface. This is what you need here. So,

1. you need to make TOP an interface and
2. you need to add the keyword virtual to your task: task myTask(input virtual TOP T);

There are restrictions on an interface, however. (We are not quite using it for its normal purpose here.) The main one which might affect you is that you cannot instantiate a module inside an interface.

---

https://www.edaplayground.com/x/SM33

interface TOP;
  task T;
    $display("TOP.T");
  endtask
endinterface

module tb();

  TOP TIPTOP(), TIPITTYTOP();

  task myTask(input virtual TOP T);
    begin
        T.T;
    end
  endtask
  
initial begin
  
  myTask(TIPTOP);
  myTask(TIPITTYTOP);
  
end
  
endmodule