Multiplexer is not simulating changes

Question

I am pretty new in FPGAs and I am trying to implement a MUX at the moment.

Currently my Code looks like this

entity mux4x1 is
    Port ( S : in std_logic_vector(1 downto 0);
           E : in std_logic_vector(3 downto 0);
           Y : out std_logic);
end mux4x1;

architecture Behavioral of mux4x1 is
signal outputBuff: std_logic;
begin
        Y <= outputBuff; 
        with S select
        outputBuff <=   E(0) when "00",
                        E(1) when "01",
                        E(2) when "10",
                        E(3) when "11",
                        '0' when others;
                              
end Behavioral;

Unfortunately everytime I try to simulate the code and change the values of input "S" the values of E are not changing!

When I try to create a Bitstream it shows following Error Report:

Vivado Commands
General Messages
[USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/John Bryan Valle/Documents/Vivado/Programme/Artix-7/MUX4X1/MUX4X1.sim/sim_1/behav/xsim/elaborate.log' file for more information.

[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

Synthesis
[Designutils 20-970] Unrecognized or unsupported command 'set_property IOSTANDARD LVCMOS33 [get_ports {E[2]}}]' found in constraint file. ["C:/Users/John Bryan Valle/Documents/Vivado/Programme/Artix-7/Lab-1/Lab 1 Full Adder/BASYS 3/Full_Adder_2.xdc":55]

Implementation
Design Initialization
[Designutils 20-970] Unrecognized or unsupported command 'set_property IOSTANDARD LVCMOS33 [get_ports {E[2]}}]' found in constraint file. ["C:/Users/John Bryan Valle/Documents/Vivado/Programme/Artix-7/Lab-1/Lab 1 Full Adder/BASYS 3/Full_Adder_2.xdc":55]

Place Design
DRC
Pin Planning
IO Standard
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 14. For example, the following two ports in this bank have conflicting VCCOs:  
E[2] (LVCMOS18, requiring VCCO=1.800) and E[0] (LVCMOS33, requiring VCCO=3.300)

[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.

Thank you in Advance! :)

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Answer 1

When your data type is not the bit type, you should use its library. You have used std_logic_vector data type. So you need to call the implementing library of it. The library is called std_logic_1164. Also, there is no need to define an intermediate buffer, but its presence is not a problem

library IEEE;
use IEEE.std_logic_1164.all

entity mux4x1 is
  Port ( S : in  std_logic_vector(1 downto 0);
         E : in  std_logic_vector(3 downto 0);
         Y : out std_logic);
end mux4x1;

architecture Behavioral of mux4x1 is
begin
    with S select
    Y <=   E(0) when "00",
           E(1) when "01",
           E(2) when "10",
           E(3) when "11",
           '0'  when others;
                              
end Behavioral;