I can't find an example in doc to convert a VHDL code to Verilog with icarus. I found how to do verilog to VHDL here. I tried to modify the command to do VHDL convertion on this code :
$ iverilog -tvlog95 -o button_deb.v button_deb.vhdl
button_deb.vhdl:3: syntax error
I give up.
But I've got a syntax error. Is my VHDL code is wrong ? Or is it iverilog command that is wrong ?
It seems that some support has arrived in the meantime (mainly using -g2005-sv
, -g2009
, or -g2012
switch) . Try this:
iverilog -g2012 -tvlog95 -o button_deb.v button_deb.vhd
If you pay closer attention to the output you'll see that in this way you'll loose the two generic
at the entity interface. Using vhdlpp
directly could be useful:
/path/to/vhdlpp button_deb.vhd > button_deb.v