VHDL found '0' definition of operator "+" cannot determine exact overloaded matching definition for "+"

Question

I have the problem that this line B1 <= (-c1 * (A3 + A1) + A3 + A2 - A1); keeps showing up as an error. I am aware that this problem already exists on stackoverflow, but none of the solutions have helped me. I've already created the project from scratch, which didn't help either. I don't know what to do next and I hope someone can help me here.

thanks in advance

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_signed.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;



entity ParallelAdaptor is
    Port ( A1 : in STD_LOGIC;
           A2 : in STD_LOGIC;
           A3 : in STD_LOGIC;
           c1 : in STD_LOGIC;
           B1 : out STD_LOGIC;
           B2 : out STD_LOGIC;
           B3 : out STD_LOGIC);
end ParallelAdaptor;

architecture Behavioral of ParallelAdaptor is

begin

    B1 <= (-c1 * (A3 + A1) + A3 + A2 - A1);


end Behavioral;

Answer 1

I think STD_LOGIC is a single bit (my vhdl experiences are ~20 years ago) and you can't do these kind of operations on it. So you need at least an output that can hold the result... And output B2 and B3 is not used...

I suggest you should try something from here https://www.nandland.com/vhdl/tutorials/tutorial-introduction-to-vhdl-for-beginners.html