Make two 8 bits signal join eachother to a 16 bit signal in VHLD

Question

I have a problem with combininig 2 signals. RS232 sends me a number 4 (8 bit) en then 5 (8 bit), togehter it is the number 45. My questions is how can I combine these number 4 and 5 to a 16 bit signal with the number 45 in vhdl? Also I have tried to count the two 8 bits signal and resized it but then i get a 16 bit signal with the number 9.

Answer 1

Something like the state machine bellow may help you if the idea is to gather both numbers in a single signal.

process(clk, rst)
begin 
if (rst = '1') then
     current_state <= FIRST_N;
     this_register <= (others => '0');
elsif rising_edge(clk) then
    case current_state  is 
    when FIRST_N => 
        this_register   <= RS232_input * 10; 
        current_state   <= SECOND_N;
    when FIRST_N => 
        this_register   <= RS232_input + this_register; 
        current_state   <= FIRST_N ;                   
     end case;
end if;   
end process;

Would something like this solve your problem?