I have the following entity, core, containing one of my components, generator. I pass generator a signal that is made from the sum of the generic m_r of core and the signal start of core.
However upon trying to compile this, I get the error error: no actual for constant interface "m_r" pointing me to the line generator_imp : generator. I assume it has something to do with start_generator being composed of m_r, however even after googling for a few hours, I have been able to find very little related to this specific problem. Has anyone encountered something like this before?
File the error stems from:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_components.all;
entity core is
generic (
m_r : unsigned(31 downto 0) := x"00000001";
step : unsigned(31 downto 0)
);
port (
clk : in std_logic;
reset : in std_logic;
start : in unsigned(31 downto 0);
f : out std_logic
);
end core;
architecture arch of core is
signal start_generator : unsigned(31 downto 0) := x"00000000";
signal n : std_logic;
begin
start_generator <= m_r + start;
generator_imp : generator
generic map(
step => step
)
port map(
clk => clk,
start => start_generator,
reset_in => reset,
padded_message => padded_chunk,
n => n
);
end arch;
my_components package:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package my_components is
component generator is
generic (
step : unsigned(31 downto 0)
);
port (
clk : in std_logic;
start : in unsigned(31 downto 0);
reset_in : in std_logic;
padded_message : out std_logic_vector(511 downto 0);
n : out unsigned(31 downto 0)
);
end component;
end package my_components;
Additionally, the entity core is generated within another component "all" using a for generate loop, as described below. It is also part of the my_components package, but for the sake of keeping this code overseeable I have removed it after thouroughly checking that all port names in the component match the entity. The for-generate loop works like below:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_components.all;
entity all is
port (
clk : in std_logic
);
end all;
architecture Behavioral of all is
constant count : integer := 5;
type f_array is array (0 to count -1) of std_logic;
signal f_signals : found_array;
signal reset : std_logic := '0';
signal start : unsigned(31 downto 0) := x"11111111";
begin
generate_cores : for I in 1 to mining_core_count - 1 generate
core_imp: core
generic map(
m_r => to_unsigned(I,32),
step => to_unsigned(count, 32)
)
port map(
clk => clk,
reset => reset,
start => start,
f => f_signals(I)
);
end generate;
core_zero : core
generic map(
m_r => x"00000000",
step => to_unsigned(count, 32)
)
port map(
clk => clk,
reset => reset,
start => start,
f => f_signals(0)
);
end Behavioral;
Could this be cause by the fact that signal 'start_generator' is an arithmetic operation on a concurrent part? This could cause this signal be seen as non-constant or stable as an input port. Just thinking loud..