NAND gate not working properly in this HDL?

Question

Whenever I input a = 1 and b = 1 I still get 0 and my inner pin of aAndNotb shows 1, however if I delete the Not gate I get a normally functioning Nand gate, what's the deal?

/**
 * And gate: 
 * out = 1 if (a == 1 and b == 1)
 *       0 otherwise
 */

CHIP And {
    IN a, b;
    OUT out;

    PARTS:
    // Put your code here: 
    Nand(a=a, b=b, out=aAndNotb);   
    Not(in=aAndNotb, out=out);
}

Answer 1

Given the symptoms you describe, the problem appears to be in your Not gate. Perhaps that component is not correctly implemented?

You can test this by implementing the Not gate directly using a Nand gate, which if you've implemented a Not gate, you already know how to do.

If that works, then the issue is the Not gate implementation. If it doesn't, then the issue is the wiring of the gates for some reason (but they look OK to me).