Nested if (rising_edge(clk)) statements in VHDL

so I’ve come across some old code that I have to replicate, but it won’t compile with the new Xilinx compiler, so I need to figure out exactly what it does. I have something like this:

if rising_edge(clk) then
   —do some things
   if rising_edge(clk) then
      —do some other things
   end if
end if

Does it take 2 clock cycles to get to the inner if statement, or is the second if statement simply redundant?

Also, Xilinx gives the error: “Logic for signal is controlled by a clock but does not appear to be a valid sequential description”

Thanks, and any help is appreciated.

Solution

If it synthesized before it was a synthesizer failure/bug. How sure are you that the code matches what was tested and determined to be working? (It sounds like you only have someone's word for this being the correct code that was synthesized before.)

Is the existing system available for comparison and testing? What are the tool versions involved? Can you use the old tools and verify it synthesizes and what warnings it provides? Depending on what version you are using you might be able to use the synthesis report, fpgaeditor (or similar) to look at what actually synthesized.
Or you can analyze the code to see what the designer intended and duplicate that with valid HDL.

Failing that all you have left is trial and error. Try assuming:

The statements inside the nested rising edge are always active. (Remove the nested rising edge if statement leaving the code block it surrounded).
The statements inside the nested rising edge are never active. Remove the entire nested rising edge block.
You could try it but I really can't imagine how a synthesizer would create a 2 cycle delay out of this. You might be reduced to trying this or other even more unlikely situations. It gets really hard to predict what this failure mode would be.