What FPGA vendor boards are supported (well) by Chisel? Are most FPGAs on the market generically supported? Or do we need to be careful about some details when buying? If so, what should we pay attention to?
I really need a hardware suite that minimizes the gap and hassles between the simulation and the actual synthesis layer. Thanks!
Chisel produces a synthesizable subset of Verilog 2001 that is supported by all FPGAs and FPGA tool vendors.
By example, you can write Chisel code for an inverter and use this to generate Verilog:
import chisel3._
import chisel3.stage.ChiselStage
class Inverter extends RawModule {
val in = IO(Input(Bool()))
val out = IO(Output(Bool()))
out := !in
}
(new ChiselStage).emitVerilog(new Inverter)
The produced Verilog is shown here:
module Inverter(
input in,
output out
);
assign out = ~in; // @[main.scala 10:10]
endmodule
This Verilog file can then be used in any FPGA toolchain (open or closed source) that supports Verilog. You would need to write the associated collateral that the toolchain wants (implementation constraints file, etc.). Functional verification can be done a lot of ways, e.g., writing Verilog/SystemVerilog testbenches for the generated Verilog, using cocotb for Python-based testbenches, or using one of the Chisel testing libraries (which actually run tests on the Verilog) like ChiselTest. ChiselTest actually uses Verilator as one of its possible backends meaning that the tests you write in ChiselTest will run on a Verilator-compiled binary. This is a concrete example of tight coupling between generated Verilog and a tool that only ingests Verilog.
Note: this views FPGA vendor tools as "Verilog to bitstream compilers" and not as "integrated development environments". By this view, FPGA vendor tools support any of the HDLs of a similar type including, but not limited to: Clash, nmigen, and SpinalHDL. For IDE-support, a Java IDE is going to be better for doing actual Chisel development, e.g., Emacs with Scala metals or IntelliJ Idea.