Counting down unsigned numbers is missing the 9 and 8 every 10

Question

I don't know where I am going wrong, or how to fix it. I am basically building a state counter and it starts at 33 and counts down to 0 before resetting but 29,28,19,18,9 and 8 all miss. I am stuck on where I am going wrong.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


entity sequencer is
 PORT(clk:      IN  std_logic;             
        count   : out unsigned (5 downto 0)); 
End sequencer;

ARCHITECTURE behavior OF sequencer IS
SIGNAL dSig, qSig   : unsigned (5 downto 0);

BEGIN

    PROCESS (clk, dSig)  
    BEGIN 
     
     dSig <= "011011";

    if rising_edge(clk) Then
        qSig <= dSig;
    end if;
     
     if qSig = "000000" then 
       dSig <= "011011"; 
    else
       dSig <= qSig - 1 ; 
    End if;
     
     count <= qSig;
     
    End Process;
END behavior; 

Answer 1

The whole process can be simplified to

process (clk, reset)  
begin 
    if reset then -- use an asynchronous reset for initial value
        dSig <= "011011";

    elsif rising_edge(clk) Then -- keep everything else within the synchronized block
        count <= dSig;
        if dSig = "000000" then
            dSig <= "011011";
        else
            dSig <= dSig - 1 ; 
        end if;
    end if;
end process;

Work with one counter signal and keep everything within the synchronized block of your process, or is there a reason for the async output evaluation?