FSM Conditional counter

Question

I want to implement the following conditional fsm in Verilog:

for this fsm, I wrote the following specifications for the first state only but don't know how to move to the next state with following specifications, in which next state depends upon the MOVE input:

 module Peer (CLK, RESET, MOVE, STATE);
input CLK, RESET, MOVE;
output [2:0] STATE; 
reg [2:0] STATE;

parameter  HoD's_Office = 3'b000, Lab_1 = 3'001, Lab_2 = 3'b010,
       Lab_3 = 3'b011, Main_Office = 3'b100, Dean's_Office = 3'b101,
       Registrar's_Office = 3'b110, VC's_Office = 3'b111;

 
 always @ (posedge CLK)
 begin 
    if(RESET)
    STATE = HoD's_Office;
    else if(~MOVE)
    STATE = HoD's_Office;
    else
    STATE = Lab_1;
 end    

Answer 1

It is a common good practice to split an FSM into 2 always blocks:

• 1 for the current state (sequential logic)
• 1 for the next state (combinational logic)

For the next state logic, use a case statement. I show the first 2 states, as you requested, and the remaining states should be straightforward.

module Peer (CLK, RESET, MOVE, STATE);
input CLK, RESET, MOVE;
output [2:0] STATE; 
reg    [2:0] STATE;
reg    [2:0] next_state;

parameter
    HoDs_Office         = 3'b000,
    Lab_1               = 3'b001,
    Lab_2               = 3'b010,
    Lab_3               = 3'b011,
    Main_Office         = 3'b100,
    Deans_Office        = 3'b101,
    Registrars_Office   = 3'b110,
    VCs_Office          = 3'b111
;

always @ (posedge CLK) begin 
    if (RESET) begin
        STATE <= HoDs_Office;
    end else begin
        STATE <= next_state;
    end
end    

always @* begin
    case (STATE)
        HoDs_Office : next_state = (MOVE) ? Lab_1       : HoDs_Office;
        Lab_1       : next_state = (MOVE) ? Main_Office : Lab_1;
        // etc.
    endcase
end    

endmodule

---

I changed some of your parameter names; it is illegal to have a single quote in a Verilog identifier.