Suppose I do a long REP INSB reading a PCI device register from user mode in a normal-priority thread. What of the following can and what cannot happen during the time it executes:
Assume a reasonably modern processor if the anstwer would depend on it. Of interest are Atoms and Core i3.
REP INSB is interruptable in between the boundaries of each INSB instruction being executed. The state is saved in the RCX and RDI registers so after processing the interrupt the instruction can be resumed at the point it was interrupted.
The individual INSB instructions being executed by REP INSB are not interruptable, are atomic and are performed strictly in instruction order with respect to other instructions executed on the same core. This atomicity means that another core or PCI device can not perform an I/O read or write to the same I/O address while the INSB instruction executes. However, another core or PCI device can read or write to the same I/O address in between each successive execution of the INSB instruction.
Interrupts on other cores have no effect on the REP INSB instruction, except that they might cause code to execute that end ups accessing the same I/O address at the same time. Context switches can only happen on interrupts and exceptions, so a context switch is possible in between the boundaries of each INSB instruction.
So in other words, you need to ensure, through mutexes or some other mechanism, that no other thread, regardless of what core they're being run on, can access the same I/O address as the REP INSB instruction is using. Disabling interrupts would prevent other threads running on the same core from executing but won't prevent other threads from running on other cores.
In fact you're going probably have to ensure no other thread accesses the device you're using throughout the entire operation your performing, as another thread changing device registers on the same device while your REP INSB instruction executes will likely cause problems.