I am trying to make an ALU with an adder, mux2 and mux4 component with port map. I have write the ALU it pass compiling OK. The problem is when I try in modelsim to give values, the adder works ok, but the mux2 (sub_module) & mux4 (sub_module x2) don't give output. I replace 2-3 times the mux code and the problem is the same. I only get UUUUUUUU values for outY. I have minimized the code.
Main ALU minimized
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ALU7_minimal is
Port ( inpA : IN STD_LOGIC_VECTOR (7 downto 0) :="10110001";
inpB : IN STD_LOGIC_VECTOR (7 downto 0) :="00011001";
ALUS0 : in STD_LOGIC := '0';
outY : out STD_LOGIC_VECTOR (7 downto 0));
end ALU7_minimal;
architecture Behavioral of ALU7_minimal is
component sub_module
port(x,y : in STD_LOGIC_VECTOR (7 downto 0);
s: in STD_LOGIC;
z: out STD_LOGIC_VECTOR (7 downto 0));
end component;
begin
U0: sub_module port map (inpA, inpB, ALUS0, outY );
end Behavioral ;
mux2-1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sub_module is
port(x,y : in STD_LOGIC_VECTOR (7 downto 0);
s: in STD_LOGIC;
z: out STD_LOGIC_VECTOR (7 downto 0));
end sub_module ;
architecture Behavioral of sub_module is
begin
process (x,y,s) is
begin
if (s ='0') then
z <= x;
else
z <= y;
end if;
end process;
end Behavioral;
Just for future reference for others that experience the same problem (My teacher discover it): You needed to import into the modelsim all components files before you run the simulation. Paradox the adder of 1bit and 8bit was working even if I haven't import them, but the mux(2-1 /4-1) won't given any result. When I imported all the component files (and not just the main program), the ModelSim show the results correctly. Thank for your time and help guys, really appreciate.