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Makefile: Adding a single *.h dependency for multiple executables

There are many "Makefile" examples for multiple executables. After a lot of trials and errors, I found this is following as the simplest one.

CC      = gcc
SOURCES = $(wildcard *.c)
EXECS   = $(SOURCES:%.c=%)

.PHONY: all clean

all: $(EXECS)

clean:
    rm -f $(EXECS)

However, I could not find any simple example for including one "include.h" dependency for all those programs. Please, could anybody show me?

JW.

PS:

  • I have no idea about this example.

  • Thanks to @MadScientist, the answer is:

CC      = gcc
SOURCES = $(wildcard *.c)
EXECS   = $(SOURCES:%.c=%)

.PHONY: all clean

all: $(EXECS)

$(EXECS): include.h

clean:
    rm -f $(EXECS)
Solution

  • This makefile is fine if you have a set of executables, each of which is built from exactly one source file.

    In this situation you can just write:

    $(EXECS): include.h

    and you're done.