JK_FF Counter Error with illegal reference

Question

I'm making a counter with a JK_FF going 0->1->2->3->4->0

This is my Verilog code:

module JK_FF (Q, J, K, clk, rst);
output Q;
input J, K, clk, rst;
reg Q;

always @ (posedge clk or negedge rst)
    if(!rst) Q<=1'b0;
    else 
      case ({J,K})
        2'b00: Q<=Q;
        2'b01: Q<=1'b0;
        2'b10: Q<=1'b0;
        2'b11: Q<=~Q;
      endcase
endmodule

module Counter(A,B,C,JA,KA,JB,KB,JC,KC,clk,rst,in);
output A,B,C;
input JA,KA,JB,KB,JC,KC,clk,rst,in;
reg A,B,C;

JK_FF JKA(A,JA,KA,clk,rst);
JK_FF JKB(B,JB,KB,clk,rst);
JK_FF JKC(C,JC,KC,clk,rst);

always @ (posedge clk or negedge rst)
    if(in==1'b1) begin
        if(!rst) begin
            A<=1'b0;
            B<=1'b0;
            C<=1'b0;
        end
        else begin
            JA<=B&C;
            KA<=1'b1;
            JB<=C;
            KB<=C;
            JC<=~A;
            KC<=1'b1;
        end
    end
endmodule

I'm getting an error at

            JA<=B&C;
            KA<=1'b1;
            JB<=C;
            KB<=C;
            JC<=~A;
            KC<=1'b1;

program says

Error: C:/Users/hoho/Desktop/project/Counter.v(34): (vlog-2110) Illegal reference to net "JA".

How should I fix this code?

Answer 1

The error message you show is telling you that you must not use an assignment statement to assign a value to a module input.

JA is a module input, and you cannot assign to it like this:

JA<=B&C;

That is illegal. The same is true for your other inputs: KA,JB,KB,JC,KC. You need to redesign your Counter module.

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If you can clear those errors up, you will run into others. You have multiple drivers for A, B and C.