Simplifying "If" Statement of Arrayed Variables in Verilog

Question

I am using UART to input various characters (ASCII) and converting each to hex. I am using an array to store these character inputs. I'd like to simplify this potentially excessive "if" statement if possible.

My declarations:

reg [7:0] input_param [1:12]; // Array w/8-bit wide variables
localparam ASCII_0 = 8'h30;

// ASCII to Hex Conversion
always@(input_param)
  begin
    if     (input_param[1] == ASCII_0)          input_param_h[1]    =   4'h0;
    else if(input_param[1] == ASCII_1)          input_param_h[1]    =   4'h1;
    ...
    else if(input_param[1] == ASCII_F)          input_param_h[1]    =   4'hF;

This continues for the # of inputs I have allowed:

    if     (input_param[12] == ASCII_0)         input_param_h[2]    =   4'h0;
    else if(input_param[12] == ASCII_1)         input_param_h[2]    =   4'h1;
    ...
    else if(input_param[12] == ASCII_F)         input_param_h[2]    =   4'hF;
  end

Answer 1

You can use a case statement inside a for loop:

integer i;
always @* begin
    for (i=1; i<=12; i=i+1) begin
        case (input_param[i])
            ASCII_0: input_param_h[i] = 4'h0;
            ASCII_1: input_param_h[i] = 4'h1;
            //
            ASCII_F: input_param_h[i] = 4'hF;
        endcase
    end
end

case is simpler than if/else.

The for loop is simpler than 12 case statements; the loop will unroll into 12 parallel case statements.

always @* is simpler than using a sensitivity list with signals.