How can I fix the errors?

Question

I'm designing some codes of data bus-system by using ideal SRAM and CPU. I want to write memory mem[0] -> IR, and read memory IR -> mem[1], and finally write memory mem[1] -> DR.

But I'm having some problems. Here are the codes, and I'm very confused about making port of input, output, reg, wire. I'm having hard time using 2 DUTs by 1 Testbench. How can I avoid error by modifying this codes?

    module sram(addr,clk,din,dout,we);
    
    parameter addr_width = 12, word_depth = 4096, word_width = 16;
      
    input clk,we;
    input [addr_width-1:0] addr;
    input [word_width-1:0] din;
    output [word_width-1:0] dout;
    
    reg [word_width-1:0] mem [0:word_depth-1];
    reg [word_width-1:0] dout;
    
    always @(posedge clk) begin
        if(!we)
            mem[addr] <= din[word_width-1:0];
        end
    
    always @(posedge clk) begin
        #1 dout <= mem[addr];
     end
    
    endmodule
    
                                    
    module cpu(clk,load,reset,select,ir,dr,ac,ar,pc,addr,we);

input clk,reset;
input [1:0]select;
input [1:0]load;

output reg[15:0] ir,dr,ac;
output reg[11:0] ar,pc;

input we;
input [11:0] addr;

reg[15:0] din;
wire[15:0] dout;

sram sram(addr,clk,din,dout,we);

always @ (posedge clk or negedge reset) begin
    if(!reset) begin
        ar <= 12'b0;  ir <= 16'b0;  pc <= 12'b0;  dr <= 16'b0;  ac <= 16'b0;
    end
    
    if(select==2'b01 && load==2'b01 && we==1)
        ir[15:0] <= dout[15:0];
    else if(select==2'b01 && load==2'b10 && we==0)
        din[15:0] <= ir[15:0];
    else if(select==2'b10 && load==2'b01 && we==1)
        dr[15:0] <= dout[15:0];
    end
    
endmodule


module tb_cpu();
parameter addr_width = 12, word_depth = 4096, word_width = 16;

reg clk,reset,we;
reg [1:0]select;
reg [1:0]load;
reg [addr_width-1:0] addr;
wire [word_width-1:0] ir,dr,ac;
wire [word_width-5:0] ar,pc;
integer file_pointer;
integer file_pointer2;

cpu cpu(clk,load,reset,select,ir,dr,ac,ar,pc,addr,we);

always #5 clk = ~clk;

initial begin
    clk = 0; addr = 12'b0; we = 0; reset = 1;
    #2 reset = 0; #2 reset = 1;
    
    $readmemb("sram.dat", tb_cpu.cpu.sram.mem);
    
    file_pointer = $fopen("reg.dat");
    file_pointer2 = $fopen("memory.dat");
    
    #10 select = 2'b01; load = 2'b01; we = 1; addr = 12'b000000000000; //cycle 1
    #10 select = 2'b01; load = 2'b10; we = 0; addr = 12'b000000000001; //cycle 2
    #10 select = 2'b10; load = 2'b01; we = 1; addr = 12'b000000000001; //cycle 3
    
    $fdisplay(file_pointer, "AR = %b", tb_cpu.cpu.ar);
    $fdisplay(file_pointer, "IR = %b", tb_cpu.cpu.ir);
    $fdisplay(file_pointer, "PC = %b", tb_cpu.cpu.pc);
    $fdisplay(file_pointer, "DR = %b", tb_cpu.cpu.dr);
    $fdisplay(file_pointer, "AC = %b", tb_cpu.cpu.ac);
    
    $fdisplay(file_pointer2, "mem[0000 0000 0000] = %b",tb_cpu.cpu.sram.mem[000000000000]);
    $fdisplay(file_pointer2, "mem[0000 0000 0001] = %b",tb_cpu.cpu.sram.mem[000000000001]);
    $fdisplay(file_pointer2, "mem[0000 0000 0010] = %b",tb_cpu.cpu.sram.mem[000000000010]);
    
     $fclose(file_pointer);
     $fclose(file_pointer2);
    
    #10 $finish;
end    
endmodule

Answer 1

I get compile errors for your code in the tb_cpu module regarding the tb_cpu.sram hierarchical specifier. You should change all:

tb_cpu.sram

to:

tb_cpu.cpu.sram

For example, change:

$readmemb("sram.dat", tb_cpu.sram.mem);

to:

$readmemb("sram.dat", tb_cpu.cpu.sram.mem);

---

After I fix those compile errors, I also see compile warnings related to addr and we. I think you need to add addr and we input ports to the cpu module, with proper connections.

Module cpu:

module cpu(clk,load,reset,select,ir,dr,ac,ar,pc,addr,we);

parameter addr_width = 12, word_depth = 4096, word_width = 16;

input we;
input [addr_width-1:0] addr;

Module tb_cpu:

cpu cpu(clk,load,reset,select,ir,dr,ac,ar,pc,addr,we);