Why there is no MEM.flush in pipeline for exceptions?

Question

Here is img of RISC-V pipeline with flush for exceptions

I have question on pipeline flush for exceptions. In RISC-V, there is IF.flush, ID.flush and EX.flush in pipeline for exceptions. But I wonder why there is no MEM.flush in pipeline for exceptions. I think that if we detect the exception in MEM stage (ex. Invalid Data memory access), we have to flush MEM stage to make MEM.RegWrite value 0.

Thank you.

Answer 1

These kind of diagrams are necessarily incomplete, so I wouldn't take it too seriously.

The text mentions nothing about virtual memory, address translation, load/store failures, or even instruction memory address translations & failures, etc..

Other things commonly missing in these diagrams includes:

• the capture of the pc for jal-type instructions — there's no datapath that forwards the pc to the registers.
• the change of pc from register, for jump register for jr-type — there's no data path for a register to go to the pc instructions.
• there is also nothing in these kind of diagrams for cache misses (I$ or D$)
• I already mentioned missing address translation for both data and instruction memories
• the AUIPC instruction is also missing some datapaths

So, the diagram is certainly incomplete.

There is very likely some handling of exceptions for data memory accesses (also for instruction memory accesses) — it's just not mentioned in this diagram as this diagram ignores address translation in general.