After using Verilog for a few months, I am curious what the difference is between the following:
reg [31:0] sum;
integer sum;
Since the integer is just a 32-bit value why can't you just use reg to represent it? Why might one be more efficient than the other in terms of memory usage or access time? Please let me know what you think or if you need me to expand on my question.
Example Using Integer:
integer t = 0;
always @(posedge clk) begin
if (t < 9999) t = t + 1;
else t = 0;
end
Example Using Reg:
reg[13:0] t = 14'b0; //Represent up to 16383
always @(posedge clk) begin
if (t < 9999) t = t + 14'b00000000000001;
else t = 14'b0;
end
integer sum; // is equivalent to
reg signed [31:0] sum;
At Verilog's inception in the 1980s, integer was a signed, unsized 4-state integral type. Its physical size was inferred from the simulation host tool. Synthesis tools were to infer its size from the context is was used (i.e. a for loop that would eventually get unrolled into a set of constant values).
But later versions of Verilog, and now SystemVerilog simply use integer as a 4-state signed type with a pre-defined 32-bit width. Realize that a 4-state 32-bit type actually takes up 64-bits to. hold its value.
Also note that SystemVerilog renames the reg keyword to logic because this datatype was never meant for describing registers exclusively. Also see: https://blogs.sw.siemens.com/verificationhorizons/2013/05/03/wire-vs-reg/