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driversystem-verilogsynthesis

SV: Error llegal combination of procedural drivers


Getting a SV: Error illegal combination of procedural drivers error with the below code, any idea how to resolve this? The values of temp range from 0 to 3.

    module multi_driver_check ();
    reg [7:0] ll_data_map[3:0];
    reg [7:0] data_in[3:0];
    reg [7:0] temp[3:0];
    assign data_in = '{default:0};
    genvar map_i;
    for(map_i=0;map_i<4;map_i++)
    begin
      always_comb
      begin
        if(temp[map_i]==0)
          ll_data_map[0] = data_in[map_i];
        else if(temp[map_i]==1)
          ll_data_map[1] = data_in[map_i];
        else if(temp[map_i]==2)
          ll_data_map[2] = data_in[map_i];
        else
          ll_data_map[3] = data_in[map_i];
     end 
    end
   endmodule

Solution

  • Reason for Error:
    A generate for-loop unravels the code it encapsulates with in it at elaboration time of compile. always_comb make sure that anything it assigns is not assigned anywhere else. In your code is compiled, you effectively have 4 always_combs assigning ll_data_map which is illegal.

    Solution:
    Move the for-loop inside the always_comb (map_i cannot be a genvar). This way all assignments to ll_data_map is done by a single always_comb.

    Other Note:
    ll_data_map is not a combinational logic even thought it is defined in an always_comb. The best tools will flag this; worst case it will fail to synthesize because the target devices does not support latches.
    To make it proper combinational logic, you could add ll_data_map = '{default:'0}; (or some other deterministic assignment) before starting the for-loop.
    If ll_data_map is intended to be a latch, then use always_latch instead of always_comb. (In general RTL design, latches are discouraged but are necessary for certain functionality)