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syntaxverilogfpgavivado

Verilog - "timescale"

Question:

I use "timescale" before module to regulate time, but Vivado tell me there is a syntax error at the first row. Please tell me the reason and what should I write?

Display from Vivado:

Error:Syntax Error near "".

Code:

'timescale 1ns/1ns
module datactl (data,in,data_ena);

    output [7:0] data;
    input [7:0] in;
    input data_ena;

    assign data = data_ena?in:8'bzzzz_zzzz;

endmodule
Solution

  • It looks like you used a single quote ' instead of a backtick `. A compiler directives use a backtick. Note that there's no need for the `timescale directive unless your code has #delays or specify blocks.